I'm a PhD candidate in Computer Architecture at the Universitat Politècnica de Catalunya (UPC), where I conduct my research as a member of the ARCO research group under the supervision of Prof. Antonio González and Prof. Juan Luis Aragón. My work focuses on energy-efficient mobile GPU architectures, memory-system optimization, and workload-driven performance analysis.
My research combines architectural simulation and profiling to identify microarchitectural bottlenecks and guide architecture design decisions. I have investigated novel GPU microarchitectures that improve performance while substantially reducing energy consumption. Examples include techniques that smooth main memory traffic and heterogeneous GPU architectures with specialized shader cores. In 2024, my work was recognized by the Generalitat de Catalunya with the DonaTIC Award in the doctoral student category.
Before starting my PhD, I worked on energy-aware runtime systems for HPC and AI data centers, and contributed to the design of a RISC-V-based CPU that reached tapeout.
Publications
2026
Design of a GPU with Heterogeneous Cores for Graphics
A. Tomás, J. L. Aragón, J.-M. Parcerisa, A. González
Heterogeneous architectures can deliver higher performance and energy efficiency than symmetric counterparts by using multiple architectures tuned to different types of workloads. While previous works focused on CPUs, this work extends the concept of heterogeneity to GPUs by proposing KHEPRI, a heterogeneous GPU architecture for graphics applications.
Scenes in graphics applications showcase diversity, as they consist of many objects with varying levels of complexity. As a result, computational intensity and memory bandwidth requirements differ significantly across different regions of each scene. To address this variability, our proposal includes two types of cores: cores optimized for high ILP (compute-specialized) and cores that tolerate a higher number of simultaneously outstanding cache misses (memory-specialized).
A key component of the proposed architecture is a novel work scheduler that dynamically assigns each part of a frame (i.e., a tile) to the most suitable core. Designing this scheduler is particularly challenging, as it must preserve data locality; otherwise, the benefits of heterogeneity may be offset by the penalty of additional cache misses. Additionally, the scheduler requires knowledge of each tile's characteristics before rendering it. For this purpose, KHEPRI leverages frame-to-frame coherence to predict the behavior of each tile based on that of the corresponding tile in the previous frame.
Evaluations across a wide range of commercial animated graphics applications show that, compared to a traditional homogeneous GPU, KHEPRI achieves an average performance improvement of 9.2%, a throughput increase (frames per second) of 7.3%, and a total GPU energy reduction of 4.8%. Importantly, these benefits are achieved without any hardware overhead.
@misc{tomas2026heterogeneous,
author = {Tom{\'a}s, Aurora and Arag{\'o}n, Juan L. and Parcerisa, Joan-Manuel and Gonz{\'a}lez, Antonio},
title = {Design of a {GPU} with Heterogeneous Cores for Graphics},
year = {2026},
eprint = {2601.22862},
archivePrefix = {arXiv},
primaryClass = {cs.AR},
doi = {10.48550/arXiv.2601.22862},
url = {https://arxiv.org/abs/2601.22862}
}
2024
LIBRA: Memory Bandwidth- and Locality-Aware Parallel Tile Rendering
A. Tomás, J. L. Aragón, J.-M. Parcerisa, A. González
ConferenceIn MICRO 2024 — Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture
The increasing demand for high-quality graphics requires a significant increase in computational power of modern GPUs. The common approach to follow is augmenting the number of compute units (i.e., shader cores). However, this can result in underutilized resources if the workload is not properly balanced. This is particularly challenging in Tile-Based Rendering (TBR) GPUs, the predominant architecture in mobile GPUs, running graphics applications due to limited per-tile workload.
This work proposes parallel tile rendering to efficiently increase the computational capabilities of TBR GPUs. This solves the problem of not having enough work to utilize the additional compute units but causes memory-intensive applications to underperform due to the increased memory pressure. To this end, we introduce LIBRA, a parallel tile rendering architecture that includes a novel locality-aware approach to schedule tiles to Raster Units to evenly distribute memory requests during the rendering of each frame. This alleviates memory congestion, therefore, reducing memory access time. LIBRA leverages frame-to-frame coherence to predict the memory pressure of each tile of a frame without penalizing the hit ratio of the cache memories.
Evaluations over a wide range of commercial gaming applications show that LIBRA reduces the average memory latency by 13.5% and achieves an average speedup of 20.9%. It also provides an 11.4% improvement in throughput (frames per second) and a total GPU energy reduction of 9.2%, while adding negligible overhead.
@inproceedings{tomas2024libra,
author = {Tom{\'a}s, Aurora and Arag{\'o}n, Juan L. and Parcerisa, Joan-Manuel and Gonz{\'a}lez, Antonio},
title = {{LIBRA}: Memory Bandwidth- and Locality-Aware Parallel Tile Rendering},
booktitle = {Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture (MICRO)},
year = {2024},
publisher = {IEEE},
doi = {10.1109/MICRO61859.2024.00081}
}
Honors & Awards
2026
ACACES Summer School Scholarship
HiPEAC
Scholarship to attend the ACACES Summer School, focused on high-performance computing, computer architecture, and advanced systems.
2024
DonaTIC Award — Doctoral Category (Woman in ICT)
Generalitat de Catalunya
Recognized by the Catalan government for my contributions to energy-efficient ICT research and for serving as a role model to young women.
2024
HiPEAC Paper Award
HiPEAC
Awarded by the HiPEAC network for the paper LIBRA: Memory Bandwidth- and Locality-Aware Parallel Tile Rendering, published at MICRO 2024.
2021
FPI Research Fellowship
Ministerio de Ciencia, Innovación y Universidades
Predoctoral fellowship from the Spanish Ministry of Science, Innovation and Universities.
2021 & 2020
Nacho Navarro Scholarship
Departament d'Arquitectura de Computadors · Universitat Politècnica de Catalunya
Awarded by the Department of Computer Architecture at UPC in support of master's studies.
Projects
Project · 01
Energy-Efficient GPU Microarchitectures
Research on energy-efficient GPU microarchitectures for low-power devices, identifying bottlenecks in graphics workloads and evaluating alternative design approaches. Proposed techniques to optimize memory usage and exploit workload heterogeneity through specialized shader cores.
PhD · Ongoing
Project · 02
Elpis
Designed and implemented from scratch a 5-stage pipelined, multicycle CPU based on the RISC-V ISA with selected MIPS-inspired design ideas. A reduced version of the core was taped out through Efabless Corporation's Google-sponsored Open Source Shuttle MPW-3 program.
Synthesizable Verilog multiprocessor system with a directory-based cache coherence protocol using custom Elpis processor cores.
UPC
Project · 04
Energy Aware Runtime
Contributed to a system-level energy management framework for HPC clusters as part of the BSC–Lenovo collaboration. Proposed an automatic DVFS-based control mechanism to enforce energy consumption limits by dynamically adjusting CPU frequency and voltage based on predicted workload energy consumption and cluster load.
